High-voltage normally-on SiC VJFETs offer higher efficiency than silicon transistors due to the inherent material advantages of SiC. Compared with the SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), SiC VJFETs are also more reliable due to the absence of the SiC metal-oxide-semiconductor (MOS) interface, which is of much inferior quality compared with Si MOS interface, and is known to cause problems such as threshold voltage shifting. FIG. 1A depicts applications where normally-off operation mode is preferred, wherein a high-voltage normally-on SiC JFET 104 can be connected with a low-voltage normally-off silicon (Si) MOSFET 105 in a cascode configuration, forming a cascode switch 112 that is normally-off.
FIG. 1A illustrates a schematic diagram of such a prior art cascode switch 112. The source 108 of the high-voltage SiC JFET 104 is connected to the drain 105 of the low-voltage Si MOSFET 105. Further, the gate 106 of the high-voltage SiC JFET 104 is connected to the source 111 of the low-voltage Si MOSFET 105. The drain 107 of the SiC JFET 104 becomes the drain 102 of the cascode switch 112, and the source 111 of the Si MOSFET 105 becomes the source 103 of the cascode switch 112. In the on-state, a biasing voltage needs to be applied to the gate 101 of the cascode switch to turn on the Si MOSFET 105, in order to turn on the whole cascode switch 112. In the off-state, when applying an increasing voltage to the drain 102 of the cascode switch 112, keeping the source 103 and gate 101 of the cascode switch 112 shorted, initially the source 108 voltage of the SiC JFET 104 will rise until it reaches the threshold voltage of the SiC JFET 104, at which point the voltage difference between the gate 106 and the source 108 of the SiC JFET 104 turns the JFET 104 off. As a result, the low-voltage Si MOSFET 105 only supports the threshold voltage of the SiC JFET 104, and the rest of the voltage that is applied between the drain 102 and the source 103 of the cascode switch 112 is supported by the high-voltage SiC JFET 104.
The prior art of the aforementioned cascode switch integrates the high-voltage normally-on switch with the low-voltage normally-off switch at the package level. FIG. 1B illustrates an example of the prior art where the cascode switch 113 is assembled using die stacking The low-voltage Si MOSFET die, consisting of the Si chip 120, the drain electrode 119, the source electrode 121, and the gate electrode 122, sits directly on top of the SiC JFET die, consisting of the SiC chip 116, the drain electrode 115, the source electrode 118, and the gate electrode 117. The source 118 of the SiC JFET and the drain 119 of the Si MOSFET is connected by direct contact of the two dies. But the gate electrode 117 of the SiC JFET has to be connected to the source electrode 121 of the Si MOSFET using external connection 113. The conducting lead frame 114 on which the stacked dies sit serves as the drain of the cascode switch 113. The gate 122 of the Si MOSFET serves as the gate of the cascode switch 113, and the source 121 of the Si MOSFET as the source. The cascode switch assembled at the package level requires complicated assembly procedures, which increases manufacturing cost and reduces reliability. It also introduces high undesirable parasitic inductance, capacitance and resistance, which can cause slow switching, reduced efficiency, and ringing during switching transients.
The invention described herein integrates the SiC JFET with the Si MOSFET into the monolithically integrated cascode switch at the wafer level. This invention simplifies the assembly compared with the die stacking prior art and reduces parasitic components at the same time. Further, Si-IC smart features can be built monolithically into the cascode structure to add functionalities such as switching speed control, short circuit turn-off, dynamic overcurrent limiting. The gate driver for the SiC VJFET can also built monolithically using the integrated Si.